The work discussed in my Ph.D thesis is based on and extended from the publications listed below (requires user-id and passwd):

• Johanna Tuominen, Tomi Westerlund and Juha Plosila. Feasibility Report on Formal Area Complexity Estimation. In TUCS Technical Report 907, Turku Centre for Computer Science, Finland, pages 1-40, August 2008. PDF
• Johanna Tuominen, Tomi Westerlund and Juha Plosila. Power Aware System Refinement. Electronic Notes in Theoretical Computer Science (ENTCS), volume 201C, pages 223-253, 2008. PDF
• Johanna Tuominen, Tomi Westerlund and Juha Plosila. Formal Power Analysis of On-Chip Communication. In Brasilian Symposium on Formal Methods (SBMF) , pages 87-102, 2007. PDF
• Johanna Tuominen, Tero Säntti and Juha Plosila. Towards a Formal Power Estimation Framework for Hardware Systems. In International Symposium on System-On-Chip , pages 96-99, 2005. PDF
• Johanna Tuominen and Juha Plosila. Formal Specification of an Asynchronous Viterbi Decoder. In 23rd IEEE Norchip Conference, pages 214-217, 2005. PDF